In memory components, in particular semiconductor memory components, a distinction is made between so-called functional memory components, e.g., PLAs, PALs etc. and so-called tab memory components, e.g., ROM components (ROM=Read Only Memory), for example PROMs, EPROMs, EEPROMs, and Flash-memories, and RAM components (RAM=Random Access Memory), e.g., DRAMs or SRAMs (D=dynamic, S=static).
A RAM component is a memory device in which data is stored under a specific address, from which the data can be read later. In a high density RAM component it becomes important for the manufacturing of the individual cells to be kept as simple as possible.
With so-called SRAMs (SRAM=Static Random Access Memory) the individual memory cells for instance consist of a few transistors, and in so-called DRAMs (DRAM=Dynamic Random Access Memory) of only a single suitably controlled capacitance (e.g., the gate source capacitance of a MOSFET), with which in form of a charge one bit at a time can be stored. In the case of DRAMs, this charge only persists for a short period of time, which means that a so-called “refresh” process must be performed at frequent intervals (e.g., 64 ms).
In contrast, in the case of SRAMs, the charge does not need to be refreshed, i.e., the respective data remains stored in the cell as long as a supply voltage is fed to the SRAM non-volatile memories, such as ROM components (ROM=Read Only Memory) as well as PROMs, EPROMs, EEPROMs, and FLASH memories, are memory components in which the respective data remains stored even after the supply voltage is turned off.
In general, during the normal use of a ROM component, no write operations but only read operations are performed. Just as is the case for RAMs, the typical read access time, and the time it takes to write data onto the ROMs may differ between the different types of non-volatile memories.
The majority of non-volatile memories are based on charge storage and these devices are fabricated from materials available in CMOS processes (CMOS=complementary metal-oxide semiconductor). However, these memory concepts based on charge storage have some general drawbacks like high voltage operation (10-20V), slow programming speed (between μs and ms) and a limited programming endurance (typically 105-106 write/erase cycles). Due to the required high voltages, high power consumption is needed for programming and erasing FLASH memories.
These shortcomings are caused by the requirement of long term data retention, which necessitates the existence of a large energy barrier that has to be overcome during programming and erasing the memory cell. The existence of such an energy barrier thus severely limits the performance and the scalability of these devices. These facts imply several severe restrictions regarding the system design. Thus, the major advantage of FLASH memory is its non-volatility and its small cell size, making FLASH memory well suited for high density memories combined with low manufacturing costs per bit.
In addition to the memory components mentioned above, so-called “resistive” or “resistively switching” memory devices have also become known recently, e.g., so-called Perovskite Memories, PMC Memories (PMC=Programmable Metallization Cell), Phase Change Memories, OUM memories (OUM=Ovonics or Ovonyx Unified Memories), hydrogenised, amorphous silicon memories (a-Si:H memories), polymer/organic memories, etc.
Perovskite memory cells are, for instance, known from S. Q. Liu et al., Appl. Phys. Lett. 76, 2749, 2000, and for example from W. W. Zhuang et al., IEDM 2002, etc. Polymer/organic memory cells (e.g., charge-transfer-complex-based polymer/organic memory cells) are for example described in X. Wan et al., Phys. Stat. Sol. A 181, R13, 2000.
In a PMC memory, during the programming of the cell, a metallic dendrite between respective electrodes—depending on whether a logic “1”, or a logic “0” shall be written into the cell—is either built up, or dissolved. Thus, the contents of the PMC memory is defined by the respective resistance between the electrodes.
The resistance between the electrodes is controlled by suitable current or voltage pulses applied to electrodes arranged at the PMC memory, thereby causing suitable electrochemical reactions which lead to the building up or dissolution of the above-mentioned metallic connection between the electrodes. Such programmable metallization cells (PMC) comprise an electrolyte material layer of so-called chalcogenide material enriched with, e.g., Ag or Cu which is capable of electrochemical reactions due to externally applied voltage or current pulses, thereby changing the electrical resistance of the electrolyte chalcogenide material layer and the entire PMC memory.
PMC memory is, e.g., disclosed in: Y. Hirose, H. Hirose, J. Appl. Phys. 47, 2767 (1975), M. N. Kozicki, M. Yun, L. Hilt; A. Singh, Electrochemical Society Proc., Vol. 99-13, (1999) 298; in M. N. Kozicki, M. Yun, S. J. Yang, J. P. Aberouette, J. P. Bird, Superlattices and Microstructures, Vol. 27, No. 5/6 (2000) 485-488; M. N. Kozicki, M. Mitkova, J. Zhu, M. Park, C. Gopalan, “Can Solid State Electrochemistry Eliminate the Memory Scaling Quandry”, Proc. VLSI (2002); and R. Neale, “Micron to look again at non-volatile amorphous memory”, Electronic Engineering Design (2002). The contents of these documents is incorporated herein by reference.
For future mobile applications, low power consumption, non-volatility and high operation speed enabling fast data rates, are mandatory. Since charge storage memories (e.g., DRAM and floating gate memories like FLASH) are reaching their scaling limits due to data retention problems caused by inevitable charge leakage from the cells, and moreover, poor data sensing capability of the ever-decreasing amounts of stored charge, alternative electronic switching mechanisms seem superior to meet the above-mentioned requirements.
In the case of “resistive” or “resistively switching” memory devices, an electrolyte material layer comprising a chalcogenide compound is positioned between two suitable electrodes, e.g., an anode and a cathode. By appropriate switching processes, said electrolyte chalcogenide material layer can be put in a more or less conductive state. Thereby, e.g., the more conductive state may correspond to a stored logic “1” and the less conductive state may correspond to a stored logic “0”, or vice versa.
In principle, the electrolyte chalcogenide material layer of a resistively-switching memory cell comprises a host matrix material and metallic material incorporated or deposited therein. The memory switching mechanism of a resistively-switching memory cell is substantially based on a variation of the concentration of metallic material incorporated in the host matrix material, which can be a chalcogenide glass for example. The resistivity of the host matrix material can vary over orders of magnitudes from a high resistivity (i.e., exhibiting an insulating or semiconducting behaviour) to low resistivity values, which are lower by several orders of magnitude. This huge resistance change is caused by local variations of the chemical composition on a nanoscale structure.
In addition to the formation of a dendritic pathway in the above mentioned PMC memory cells, the resistive switching mechanism can also be caused by the statistical bridging of multiple metal rich precipitates. Upon continued application of a write pulse to the resistively-switching cell, the precipitates grow in density until they eventually touch each other, forming a conductive bridge through the entire memory cell, which results in a highly conductive, metallic or semiconducting connection between the two electrodes of the memory cell. This corresponds to a percolation mechanism including the formation of precipitates, which are present in the electrolyte chalcogenide material layer, leading to an electrical bridging of the electrodes by a highly conductive connection. However, the precipitates can be sustained for long storing times, so that the non-volatility of the state can be guaranteed.
In addition to the existence of these precipitates, there are also metallic, semiconducting, or ionic constituents present in the electrolyte chalcogenide material layer, which are free to move therein. This movement can be stimulated, for example, by applying external electric fields to the matrix, so that an electrically induced ion drift occurs. Electrically induced movement offers the advantage that reversible concentration changes can be obtained simply by driving in and pulling out these mobile metal ions. An increased or decrease in the size of the precipitates can occur as a result of the mobility of these metallic or ionic components.
For this reason, the electrolyte chalcogenide matrix material is in direct contact with the first electrode. The second electrode, which is also in contact with the electrolyte chalcogenide material, contains the above mentioned metallic, semiconducting, or ionic constituents and exhibits the required solubility and the required high mobility within the electrolyte chalcogenide material. The first and second electrodes have neither a direct electrical contact nor an interface with each other, so that the electrolyte chalcogenide material layer separates the two electrodes. However, the electrodes can be in direct contact with other conducting or doped semiconducting materials (e.g., metal wires or metal plugs) to electrically connect the memory cell to other devices, such as transistors or other memory cells.
In the case of resistive or resistively-switching memory devices (Perovskite memories, Phase Change Memories, PMC memories, a-Si:H memories, polymer/organic memories, etc.), it is desirable to keep the layer thickness of the material positioned between the electrodes—which is correspondingly to be switched to a state of high or low conductivity—as small as possible. This makes it possible to increase the field strengths achieved in the respective material, which may result in a correspondingly high switching rate.
Various processes for depositing GeSe and GeS layers have been proposed in the state of the art. However, known GeSe layers exhibit the inherent drawback that they cannot be integrated in CMOS technology processes (CMOS=complementary metal-oxide semiconductor) and are thus not suitable for volume production because the thermal stability of the selenium-containing chalcogenide layers is not sufficient to survive the back end of line (BEOL) process temperatures (typically 400-450° C.). This is because in binary, selenium-containing materials or selenium-containing compounds the glass transition temperature and the crystallization temperature are too low. Consequently, a segregation or a crystallization, respectively, occurs in the layers, which limits or even completely destroys the functionality of the selenium-containing chalcogenide layers as a solid-state electrolyte material. In the case of binary, sulfidic compounds the intrinsic ion mobility of metal ions (e.g., silver) is too low to produce a memory cell that switches at a sufficient rate.